Parallel VLSI Architectures for Variable Block Size Motion Estimation

• Main Authors: Han-Sheng Liu, 劉瀚升
• Other Authors: Hsin-Chou Chi
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/08983155936817630201

碩士 === 國立東華大學 === 資訊工程學系 === 98 === The H.264/AVC video coding standard was recently developed by the Joint Video Team (JVT) consisting of experts from international study groups, Video Coding Experts Group (VCEG) and Moving Picture Experts Group (MPEG), which significantly improves video coding. Motion estimation is one of the core designs of the H.264/AVC video coding. Variable block size motion estimation (VBSME) is a new video coding technique which improves video distortion, provides more accurate predictions, reduces video coding data, and increases the utilization of network bandwidth. This thesis proposes parallel VLSI architectures for VBSME which apply to the full search block matching algorithm (FSBMA). Our proposed architecture use pipelined design to balance the execution time of each stage in order to increase the performance. Furthermore, our design employs parallel architectures to improve the throughput, and facilitate lower computation time. With the pipelined design, the processing elements use hierarchical structures to calculate seven kinds of blocks (4×4, 8×4, 4×8, 8×8, 16×8, 8×16, and 16×16), which have relatively simple circuits and relatively low computation complexity. We use cell-based design with TSMC 0.18 μm CMOS technology to implement our hardware. Our proposed architecture is realized with physical design flow to show its feasibility. Experimental results show that our proposed parallel architectures can increase the performance and reduce the computational complexity compared to other designs.