Design, Implementation and Verification of Single-Input-Multiple-Output Doubly Selective Channel Emulator with FPGA
碩士 === 國立中央大學 === 通訊工程研究所 === 98 === In this thesis, we design and implement a real-time single-input-multiple output frequency and time selective channel emulator with FPGA. The architecture of the channel emulator is flexible in setting system parameters such as delay-spread profile, angle-of-arr...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28622902947705557401 |
| Summary: | 碩士 === 國立中央大學 === 通訊工程研究所 === 98 === In this thesis, we design and implement a real-time single-input-multiple output frequency and time selective channel emulator with FPGA. The architecture of the channel emulator is flexible in setting system parameters such as delay-spread profile, angle-of-arrival profile and maximum normalized Doppler shift for emulating various environments. The effectness of this channel emulator is verified by observing the performance variation when emulating multiple antenna reception and diversity signal processing of OFDM signal in mobile environment。
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