Fabrication and Electrical Characterizations of Single Electron Transistor in Vertical and Planar Structures
碩士 === 國立中央大學 === 電機工程研究所 === 98 === Single-electron transistors （SETs） have attracted a lot of attention for its potential advantages of high charge sensitivity and low power consumption, which would offer great potentials for memory-devices, logic-devices and quantum computing in the future. In th...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/37653271874448508442 |
| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 98 === Single-electron transistors （SETs） have attracted a lot of attention for its potential advantages of high charge sensitivity and low power consumption, which would offer
great potentials for memory-devices, logic-devices and quantum computing in the future. In this thesis, we have studied the fabrication and electrical characterization of Ge QD SETs in vertical and planar structures. We are able to bridle the position and the number of Ge QDs by oxidizing poly-SiGe in a nano-cavity. The Ge QDs are
self-aligned to adjacent electrides via SiO2 or Si3N4 spacers, which also behave as tunnel barriers and whose thickness are directly determined by the thin-film deposition in CVD.
|
|---|