| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 98 === Yield and reliability are two very critical challenges for modern random access memories (RAMs). With the shrinking transistor size and aggressive design rules, RAMs are easily prone to severe yield and reliability problems. Therefore, efficient reliability-enhancement and yield-enhancement techniques are imperative for modern RAMs. Memory diagnosis is a widely used technique for the enhancement of memory design or manufacture process such
that the yield and reliability of the memory design are increased. Built-in self-diagnosis (BISD) technique has been widely used for the diagnosis of embedded RAMs.
A BISD design typically exports diagnostic data serially through a single output. For a system-on-chip (SOC), many RAM cores exist. Thus, the amount of diagnostic data may be
very huge. To reduce the exportation time of diagnostic data, data compression technique can be applied. In this thesis, three diagnostic data compression techniques are proposed. First, a multi-level compression scheme for multiple homogeneous RAMs is proposed. The multilevel
compression scheme for multiple homogeneous RAMs can efficiently reduce diagnostic data and the area cost for realizing the compression circuit is very small. Experimental results show that if a 256-bit Hamming syndrome is partitioned into 8-bit symbols, the average compression ratio (the ratio of the number bits of the compressed data to that of the original data) is about 11% for three 128k-bit homogeneous memories. A BISD with the
multi-level compressor has been realized using TSMC 0.18-um technology. The total gate count of the proposed BISD circuit for three 8K×16 homogeneous memories is 2126, i.e., the area overhead of the BISD circuit is about 0.84%.
In addition, a March-element-based (MEB) diagnostic data compression scheme for RAMs with static and dynamic faults is proposed. The MEB diagnostic data compression
scheme can efficiently compress diagnostic data of a RAM tested by a March test for detecting static and dynamic faults. Experimental results show that the average compression ratio is about 36.08% for a 512×256-bit memory tested with 100% single cell fault by March-DD algorithm. A BISD with the MEB compressor has also been designed using
TSMC 0.18-um technology. The area overhead of the BISD is about 2.03% for an 8K×64-bit RAM.
Finally, a diagnostic data compression using faulty-bit encoding (FBE) scheme for RAMs is proposed. The FBE scheme can greatly improve compression ratio for a RAM with
different fail patterns. Experimental results show that the FBE scheme has good CR for a RAM with different fail patterns. The average CR is about 8.09% for a 512×256-bit RAM. A BISD with FBE compressor has been implemented using TSMC 0.18-um technology. The gate count of the proposed BISD for an 8K×64-bit memory is 6761, i.e., the area overhead of the BISD circuit is about 2.17%.
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