An Energy-Efficient Programmable Vertex Processor Design and Implementation for Biomedical Applications
碩士 === 國立交通大學 === 多媒體工程研究所 === 98 === In this work, an energy-efficient programmable vertex processor for biomedical application is presented. The proposed biomedical-oriented vertex processor architecture employs four techniques: 1) 24-bit floating-point precision arithmetic; 2) instruction-level p...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00800077619159512320 |
| Summary: | 碩士 === 國立交通大學 === 多媒體工程研究所 === 98 === In this work, an energy-efficient programmable vertex processor for biomedical application is presented. The proposed biomedical-oriented vertex processor architecture employs four techniques: 1) 24-bit floating-point precision arithmetic; 2) instruction-level partition with clock control and operand isolation; 3) multilevel pre-TnL vertex cache and fully-associative post-TnL vertex cache; 4) simplified parallel EEG mapping computation. From the chip implementation result in UMC 90nm CMOS process technology, the proposed vertex processor is capable of providing the energy-efficiency of 431 Kvertices/mJ.
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