Constructing Low-Density Parity-Check Codes with Hierarchical Elimination Algorithm
碩士 === 國立交通大學 === 電機學院碩士在職專班電機與控制組 === 98 === The main advantage of Low-Density Parity-Check codes is that they provide near-channel capacity decoding efficiency and are suitable for parallel approach implementation. We are most interested in the research topic which aims to enhance decoding efficie...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22623292541232484348 |
| Summary: | 碩士 === 國立交通大學 === 電機學院碩士在職專班電機與控制組 === 98 === The main advantage of Low-Density Parity-Check codes is that they provide near-channel capacity decoding efficiency and are suitable for parallel approach implementation. We are most interested in the research topic which aims to enhance decoding efficiency in codes with large girth. The most important concept is to enhance error correction capability by eliminating short cycles in a parity-check matrix expanded from a small base matrix. In this thesis, we propose a hierarchical elimination algorithm to expand and break short cycles by searching for an element that contains the largest number of short cycles and identifying the proper cyclically shifted values. According to our experimental data the hierarchical elimination method can eliminate short cycles with a very low expanding value. In addition, the hardware parallelism can be increased with multiple modules and the Block-LDPC codes efficiency can still be retained.
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