Modeling Settling Noises and Distortions for Single-Loop Sigma-Delta Modulators
碩士 === 國立交通大學 === 電機與控制工程系所 === 98 === Switch-capacitor (SC) integrators have been widely used in sigma-delta modulators ( Ms) and the performances of SC integrators depend highly on their incomplete charge-transfer (settling problem) behavior. Therefore, the settling problem is a crucial design con...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60032136907640751111 |
| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 98 === Switch-capacitor (SC) integrators have been widely used in sigma-delta modulators ( Ms) and the performances of SC integrators depend highly on their incomplete charge-transfer (settling problem) behavior. Therefore, the settling problem is a crucial design concern in well-published switch-capacitor Ms. Due to the complexity of settling problem, analytic models for related noises and distortions are virtually non-existent. The aim of this paper attempts to explore the settling problems on single-loop Ms by employing nonlinear fitting methods and output spectrum prediction techniques. Closed forms of settling error and settling distortion models are acquired, and are represented as functions of modulator system parameters. Both behavior simulations and transistor-level-circuit simulations are employed to verify these analytical models. The results of above validation showed an appropriate level of consistence between the two simulations and our analytical models.
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