| Summary: | 碩士 === 國立交通大學 === 電控工程研究所 === 98 === In modern wire-line communication systems, the request for high speed data rate is growing. Pulse amplitude modulation(PAM) technique is a transmission technique which modulates digital data into analog amplitude. As an example of 16PAM, each voltage value represents four digital data. Under the same bandwidth limitation, PAM technique rises data rate as compared to binary transmission. In this thesis, our topic is to design high speed A/D converter and D/A converter for the transmitter(TX) and receiver(RX) for high speed pulse amplitude modulation systems. A bandwidth compensation method to implement wide bandwidth and low power amplifiers is proposed, it uses digitalized technique to design the A/D converter. Besides, we also design a bult-in testing circuit to improve testability. The design is a 5GHz 4bit A/D converter and a D/A converter, using UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process. The simulation results show that the effective number of bit is 3.9, INL and DNL are less than 0.5LSB, the power consumption of A/D converter is 33.7mW, and 18.9mW for the D/A converter. Finally, the area is 0.873mm2 (950μm × 919μm).
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