Design of a Load Adaptive Gain Adjustment Mixed-Signal Critical Mode PFC AC-DC Converter

• Main Authors: Chan, Ming-Hao, 詹茗皓
• Other Authors: Tzou, Ying-Yu
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/49099344966970650215

碩士 === 國立交通大學 === 電控工程系所 === 98 === This thesis develops a mixed-signal critical mode power-factor-correction (PFC) AC-DC converter with load adaptive gain scheduling. The peak current mode control is applied and analyzed by using the analog circuit. The voltage control loop is implemented in digital approach by using a digital notch filter and load adaptive gain adjustment to optimize the dynamic responses and maintain high power-factor (PF) with low total-harmonic-distortion (THD) in line current. This thesis analyzes the effect of the hysteresis band effect of the analog current comparator and the effect of the reference voltage in zero current detecting comparator on current command. In digital voltage loop, the proper quantization resolutions of both analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are analyzed and determined. The digital voltage controller uses a digital notch filter to achieve fast dynamic response and still maintain low THD with high PF. An adaptive gain sheduling is applied for achieving the optimal dynamic response of the output voltage at different load variation conditions. The proposed mixed-signal PFC AC-DC converter with load adaptive gain scheduling has been verified by using computer simulation software (PSIM). This thesis uses the DSP EVM board TMS320LF2407 from Texas Instrument and the CRM PFC IC L6561 from STMicroelectronics to implement the experimental verification. The simulation and experimental results can verify the viability and effectiveness of the proposed control architecture.