Low-Noise Receiver/ Up- Converter Using V-NPN BJT/ Schottky Diode n Standard CMOS Process,
碩士 === 國立交通大學 === 電信工程研究所 === 98 === This thesis includes three parts. First, we realize a receiver by utilizing CMOS 0.18μm parasitic vertical BJTs in the mixer LO core to reduce flicker noise for the low-power Wireless PAN RF front-end. In the mean time, we implement a fully-integrated 60GHz up-co...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/03492272205211674452 |