Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory

碩士 === 國立交通大學 === 電子研究所 === 98 === In this thesis, we discuss the feasibility of TFT SANOS memory devices in three dimension-integrated circuits (3D-ICs). For 3D-ICs, low temperature fabrication process is necessary. Therefore, one stacked conventional SONOS devices on poly-Si films, them the design...

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Main Authors: Huang, Kuo-Chin, 黃國欽
Other Authors: Sze, Simon
Format: Others
Language:en_US
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/64054279865918476560
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spelling ndltd-TW-098NCTU54281592016-04-18T04:21:48Z http://ndltd.ncl.edu.tw/handle/64054279865918476560 Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory 五十奈米線寬薄膜型SANOS快閃記憶體的製作與特性分析 Huang, Kuo-Chin 黃國欽 碩士 國立交通大學 電子研究所 98 In this thesis, we discuss the feasibility of TFT SANOS memory devices in three dimension-integrated circuits (3D-ICs). For 3D-ICs, low temperature fabrication process is necessary. Therefore, one stacked conventional SONOS devices on poly-Si films, them the designation of thin film transistor (TFT) SONOS devices. The dimensions of TFT SANOS devices were scaled down to sub-50 nm in order to increase the chip density and memory bits. In first part, for the fabrication of sub-50nm TFT SANOS devices, we used Al2O3 to replace TEOS for the blocking layer of SONOS structure, as named SANOS structure. This layer could prevent gate injection (gate leakage current) and improve device retention ability. For electrical measurement, there are two advantages of TFT SANOS devices that could be addressed. One is that the tri-gate structure enhances the electrical field during programming and erasing periods. The other one is that there are no grain boundaries inside the channel of nanometer TFT SANOS devices. Due to the advantages, the quasi-FinFET SANOS devices get similar electrical characteristics as bulk-Si SONOS devices. These devices also have good reliability characteristics, with a memory window of 2.6V in ten years at 150OC. The second part was about microwave oxidation, we used a microwave system to grow a pure SiO2 layer at low temperature. One would like to use microwave oxide as the thermal tunneling oxide of TFT SANOS devices. In this study, we used microwave susceptors and silicon carbide wafers to enhance microwave oxidation, which causes more suitable temperature process with better microwave distribution. During a series experiments, one get a about 3.6 nm thick oxide layer. As compared with that by furnace, the oxide quality by microwave anneal was about the same as that by thermal process. But, the uniformity of microwave oxidation still needs to be improved. Sze, Simon 施敏 2010 學位論文 ; thesis 63 en_US
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language en_US
format Others
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description 碩士 === 國立交通大學 === 電子研究所 === 98 === In this thesis, we discuss the feasibility of TFT SANOS memory devices in three dimension-integrated circuits (3D-ICs). For 3D-ICs, low temperature fabrication process is necessary. Therefore, one stacked conventional SONOS devices on poly-Si films, them the designation of thin film transistor (TFT) SONOS devices. The dimensions of TFT SANOS devices were scaled down to sub-50 nm in order to increase the chip density and memory bits. In first part, for the fabrication of sub-50nm TFT SANOS devices, we used Al2O3 to replace TEOS for the blocking layer of SONOS structure, as named SANOS structure. This layer could prevent gate injection (gate leakage current) and improve device retention ability. For electrical measurement, there are two advantages of TFT SANOS devices that could be addressed. One is that the tri-gate structure enhances the electrical field during programming and erasing periods. The other one is that there are no grain boundaries inside the channel of nanometer TFT SANOS devices. Due to the advantages, the quasi-FinFET SANOS devices get similar electrical characteristics as bulk-Si SONOS devices. These devices also have good reliability characteristics, with a memory window of 2.6V in ten years at 150OC. The second part was about microwave oxidation, we used a microwave system to grow a pure SiO2 layer at low temperature. One would like to use microwave oxide as the thermal tunneling oxide of TFT SANOS devices. In this study, we used microwave susceptors and silicon carbide wafers to enhance microwave oxidation, which causes more suitable temperature process with better microwave distribution. During a series experiments, one get a about 3.6 nm thick oxide layer. As compared with that by furnace, the oxide quality by microwave anneal was about the same as that by thermal process. But, the uniformity of microwave oxidation still needs to be improved.
author2 Sze, Simon
author_facet Sze, Simon
Huang, Kuo-Chin
黃國欽
author Huang, Kuo-Chin
黃國欽
spellingShingle Huang, Kuo-Chin
黃國欽
Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
author_sort Huang, Kuo-Chin
title Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
title_short Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
title_full Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
title_fullStr Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
title_full_unstemmed Fabrication and Characterization of sub-50nm Thin Film SANOS Flash Memory
title_sort fabrication and characterization of sub-50nm thin film sanos flash memory
publishDate 2010
url http://ndltd.ncl.edu.tw/handle/64054279865918476560
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