| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 98 === In this thesis, we discuss the feasibility of TFT SANOS memory devices in three dimension-integrated circuits (3D-ICs). For 3D-ICs, low temperature fabrication process is necessary. Therefore, one stacked conventional SONOS devices on poly-Si films, them the designation of thin film transistor (TFT) SONOS devices. The dimensions of TFT SANOS devices were scaled down to sub-50 nm in order to increase the chip density and memory bits.
In first part, for the fabrication of sub-50nm TFT SANOS devices, we used Al2O3 to replace TEOS for the blocking layer of SONOS structure, as named SANOS structure. This layer could prevent gate injection (gate leakage current) and improve device retention ability. For electrical measurement, there are two advantages of TFT SANOS devices that could be addressed. One is that the tri-gate structure enhances the electrical field during programming and erasing periods. The other one is that there are no grain boundaries inside the channel of nanometer TFT SANOS devices. Due to the advantages, the quasi-FinFET SANOS devices get similar electrical characteristics as bulk-Si SONOS devices. These devices also have good reliability characteristics, with a memory window of 2.6V in ten years at 150OC.
The second part was about microwave oxidation, we used a microwave system to grow a pure SiO2 layer at low temperature. One would like to use microwave oxide as the thermal tunneling oxide of TFT SANOS devices. In this study, we used microwave susceptors and silicon carbide wafers to enhance microwave oxidation, which causes more suitable temperature process with better microwave distribution. During a series experiments, one get a about 3.6 nm thick oxide layer. As compared with that by furnace, the oxide quality by microwave anneal was about the same as that by thermal process. But, the uniformity of microwave oxidation still needs to be improved.
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