| Summary: | 博士 === 國立交通大學 === 電子研究所 === 98 === The patterned ground shield (PGS) must be well designed; otherwise they may not at all able to improve the quality factor. Investigations into different strip length, strip spacing and metal layer positions of the slot-type floating shields for wavelength, attenuation loss, and characteristic impedance, which have not yet been conducted before, are performed in this work. In general, the assumption for lumped-equivalent-circuit-model-based techniques is valid only if the lengths of the DUT devices are much smaller than the distances between two ports. However, this is not always true for larger DUT devices and may result in over de-embedding when intrinsic device performance is involved. Therefore, the proposed de-embedding technique can address the problem of over de-embedding. The contribution of the interconnection and the via stack becomes important as the frequencies increase. Unfortunately, currently existing techniques do not account for via stack parasitic contributions. In this dissertation, high-performance transmission lines and improved de-embedding techniques are presented. The slow-wave concept has been used in order to design high-performance transmission lines and reduce the size of the transmission lines. Accurate models that describe the behavior of RF devices are critical for the circuit designs, and improved parasitic de-embedding techniques are proposed as to achieve accurate device characterization.
A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide the substrate shield and shorten the electromagnetic propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length, the strip spacing, and the metal layer positions of the slot-type floating shields. Wavelength shortening needs to be achieved with a trade-off between the slow-wave effect and the attenuation loss. The slot-type floating shields with different strip lengths, strip spacings and metal layer positions are analyzed. It is concluded that the minimum strip length provides the most optimal result. A design guideline can be established that enables circuit designers to achieve the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45 nm CMOS process technology. Both measurement and electro-magnetic (EM) wave simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, improved by a factor of more than 9, and a better quality factor, improved by a factor of more than 6, as compared to conventional transmission lines.
A novel transmission line de-embedding technique is presented. With this technique, the left- and right-side ground-signal-ground (GSG) probe pads can be extracted directly using two transmission line test structures of length L and 2L. An additional through structure is designed using via stack de-embedding, which is unique amongst current de-embedding methods. The advantages of the proposed method include the following: (1) a smaller silicon area; (2) the consideration for discontinuity between the pad and interconnect; (3) the consideration for substrate coupling and contact effects; (4) the employment of via stack de-embedding; and (5) the solution to the over de-embedding. The proposed novel methodology could be considered as a breakthrough in the area of ultra-high frequency de-embedding and should enable more accurate RF models to be developed. In the proposed methodology, intrinsic slow-wave coplanar waveguide (CPW) transmission line structures are placed on the inter-level metallization layers, as they are the most appropriate RF device for a cascade-based de-embedding method involving the via stack de-embedding technique. Experimental results have demonstrated that attenuation loss and wavelength can be optimized by changing the metal density and the metal layer positions of the floating shields. With a shortened wavelength, a reduction in silicon area of more than 66% can be achieved by using optimized slot-type floating shields located both above and below the CPW structure.
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