A study on the application of Al2O3/HfO2 laminate on nonvolatile memory

碩士 === 國立交通大學 === 電子工程系所 === 98 === In this thesis, we proposed an Al2O3/HfO2 nano-laminate deposited by atomic layer deposition (ALD) method as the trapping layer of the flash type non-volatile memory. Both capacitor and thin-film transistor (TFT) structures were prepared. In order to suppress the...

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Bibliographic Details
Main Authors: Tsai, Yi-Cheng, 蔡依成
Other Authors: Tsui, Bing-Yue
Format: Others
Language:zh-TW
Published: 2009
Online Access:http://ndltd.ncl.edu.tw/handle/39889088680341178653
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Summary:碩士 === 國立交通大學 === 電子工程系所 === 98 === In this thesis, we proposed an Al2O3/HfO2 nano-laminate deposited by atomic layer deposition (ALD) method as the trapping layer of the flash type non-volatile memory. Both capacitor and thin-film transistor (TFT) structures were prepared. In order to suppress the back-side injection during erase period and to reduce the equivalent oxide thickness, high work-function gate (platinum for capacitor and P+ poly-Si for TFT) and Al2O3 blocking layer was utilized, respectively. The whole memory characteristics including memory window, program/erase speed, retention, endurance, and disturbance were evaluated and discussed in the thesis. Furthermore, the effects of process conditions, including the number of Al2O3/HfO2 nano-laminate periods, post-deposition annealing (PDA) condition, and blocking layer thickness were also studied. On the capacitor samples, a 900�aC/60sec PAD can result in a larger memory window than a 900�aC/30sec PAD. But the erase speed degrades due to crystallization of the Al2O3 blocking layer. Increasing Al2O3 blocking layer thickness from 10 nm to 20nm can strongly reduce the leakage current. Therefore, a 6V memory window after �b15V program/erase (P/E) operation for 1 sec can be achieved. About 83% of the window still remains after 105 sec. Well endurance and disturbance properties are also observed. On the TFT-memory samples, the structure of the dielectric stack is similar to that on the capacitor samples, the main difference is the SiO2 tunneling layer was replaced by Al2O3. The TFT structure exhibits faster program speed. However, because of the crystallization of the Al2O3 tunneling layer, several drawbacks such as poor retention due to charge loss through the Al2O3 tunneling layer, poor endurance, and poor gate disturbance. In conclusion, the Al2O3/HfO2 charge trapping layer proposed in this thesis exhibits good electrical performance and storage capability. The main issue of this structure would be the quality of both the tunneling and blocking layers. These layers should behave excellent thermal stability during the proceeding fabrication process and is worth further researches.