Study on the Thin Film Transistors with Various Device Structures for System-on-Panel Applications

• Main Authors: Liao, Ta-Chuan, 廖大傳
• Other Authors: Cheng, Huang-Chung
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/62163305378687657142

博士 === 國立交通大學 === 電子工程系所 === 98 === In this thesis, various structures and techniques are studied for the fabrication of high-performance low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) through drain, gate, and channel engineering. In addition, for further versatile system-on-panel (SOP) applications, the novel nonvolatile memories and field emitters based on LTPS technology are developed as well. At first, for drain engineering, the T-shaped-gate (T-Gate) LTPS TFTs with symmetric vacuum gaps have been proposed and fabricated simply only with a selective-etching technique and an in-situ vacuum encapsulation. Due to the great reduction of electric field near the drain junction by the resulting offset region and vacuum gap, the fabricated T-Gate LTPS TFTs exhibit ultra low leakage current, high on/off current ratio, reduced kink current, and high reliability. Secondly, for gate engineering, the novel gate-all-around (GAA) poly-Si TFTs with multiple nanowire channels (MNCs) have been, for the first time, fabricated using a simple process to demonstrate high performance electrical characteristics and high immunity to short channel effects (SCEs). The nanowire channel with high body thickness-to-width ratio, approximately equals to one, is realized only with a sidewall-spacer formation. Moreover, the unique suspending MNCs are also achieved to build the GAA structure. The resultant GAA-MNC TFTs show outstanding three-dimensional gate controllability and excellent electrical characteristics, which reveal a high on/off current ratio, a low threshold voltage, a steep subthreshold swing, a near-free drain-induced barrier lowering, as well as an excellent SCE suppression. For channel engineering, two types of novel processes are subsequently demonstrated for fabricating high-crystallinity Si-nanowire LTPS TFTs. The one is to utilize the previously proposed sidewall-spacer nanowire structure to control the lateral grain growth from the thicker S/D pads to the center of thinner nanowire channel. Due to the necking effect in such nanowire structure, only-one grain boundary exists in the middle nanowire channel. LTPS TFTs with field-effect mobility of 273 cm2/V-s have been fabricated by using this method. The other is to utilize spacer lithography to directly transfer the nanowire pattern onto the large-grain sequential-lateral-solidification (SLS) poly-Si thin film. In term of probability, the nanowire pattern (8 nm) is much smaller than the SLS grain width (0.8 μm), which makes the nanowire locate within a single grain, thus the resulting nanowire can be performed like a single-crystal simply. Due to the high-crystallinity formed in the nanowire channel, the nanowire TFT exhibits an excellent mobility of 596 cm2/V-s and steeper subthreshold slope of 101 mV/decade. As a result, it is very suitable for future system-on-panel (SOP) applications. For nonvolatile memory development, a field-enhanced nanowire (FEN) LTPS-TFT silicon-oxide-nitride-oxide-silicon (SONOS) memory with a gate-all-around (GAA) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently has three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carriers tunneling via such a structure lead to faster P/E speed and wider memory window for the FEN SONOS as compared to the conventional planar (CP) counterpart. The FEN LTPS TFT SONOS device exhibits a Vth shift of 2.71 V and 2.11 V at VGS = +15/-15 V in 1 ms for FN programming and erasing (P/E) operations, respectively. Other than FEN structure, a vacuum counterpart is further as a substitute for tunneling oxide to perform the novel silicon-oxide-nitride-vacuum-silicon (SONVAS) structure, for the first time. Due to the further electric field enhancement from the vacuum introduction in tunneling layer, the FEN SONVAS exhibits larger Vth shifts of 3.17V and 2.68V at VGS = +15/-15V in 1 ms for FN P/E operations, correspondingly. Besides, due to the empty property of vacuum, there are less dangling bonds and tunneling-oxide traps produced during P/E cycles, so that FEN SONVAS exhibits much improved endurance reliability as well. For field emitter development, spacer technique are applied on two types of LTPS-based field emitters for the possibilities of the replacement of LCD display elements in terms of system integration and image performance. For spacer nanowire field emitters, the F-N characteristics with turn-on field of 2.06 V/um have been performed. For the triple-corner nanowire emitter in-situ vacuum-encapsulated by the surrounding silicon dioxide, the F-N characteristics have been performed with a turn-on voltage of 0.14 V, which is the lowest one in the record to date. Finally, conclusions as well as prospects for further research are also summarized.