A Low-power Viterbi Decoder Based on Pulse Latch Survivor Memory
碩士 === 國立交通大學 === 電子工程系所 === 98 === Recently, a high-speed and low-power Viterbi decoder is needed due to wireless and portable devices. In order to reduce the power consumption of Viterbi decoder, we proposed a full-custom pulse latch as the data storage unit in the survivor memory. Because of the...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29865744463150331146 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 98 === Recently, a high-speed and low-power Viterbi decoder is needed due to wireless and portable devices. In order to reduce the power consumption of Viterbi decoder, we proposed a full-custom pulse latch as the data storage unit in the survivor memory. Because of the low-swing and the characteristic of pass transistor, the power consumption of single register is reduced, so the power of data access in survivor memory also be reduced. According to the implementation result, 29% of survivor memory power and 21% of overall decoder power could be reduced as Eb/No is 3dB.
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