A 10-Gbps Discrete-Time Adaptive Equalizer for Serial Link System

• Main Authors: Hsu, Fu-Chun, 許馥淳
• Other Authors: Jou, Shyh-Jye
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/13642041684767605368

碩士 === 國立交通大學 === 電子工程系所 === 98 === With the advance of integrated circuits (IC) fabrication technology, the operation speed of chips is becoming faster and faster. High-bandwidth I/Os have found a great demand for transferring data between chips. Many high-speed serial link transmission technologies are developed and are widely used for high performance modern electronic products. In order to maintain the signal quality that will be attenuated by communication channel, the equalizer becomes an important component in the high-speed serial link system. Since the characteristics of channel may vary due to the environment, adaptive equalizer is much preferable for long-time usage. In this thesis, we propose a 2-tap discrete-time adaptive decision-feedback equalizer that operates at 10 Gbps. We design a variable gain amplifier in the front of the proposed equalizer system to adjust the swing of input signal in the range for the following stage. A high-speed current-mode summer is designed to cancel the post-cursor ISI. A coefficient updating scheme called hopping and a mixed-signal integrator are presented to realize the mechanism of coefficients adaptation. The hopping update scheme can reduce the power consumption by slowing down the operation speed in the coefficients adaptation. The mixed-signal integrator consists of a 4-bit up/down counter and a charge pump to acquire a good performance and small area. We use the delayed sign-sign LMS algorithm to do the convergence of coefficients. The proposed equalizer is designed in a 65-nm CMOS technology. The simulation result shows that the data eye in the output of equalizer is about ±200 mVpp, and the data eye in the output of buffer stage can reach ±300 mVpp that meets our specification. The peak-to-peak jitter at the equalizer output is about 31ps. The convergence time of coefficients is about 20000 bits time. Total area of our proposed equalizer including pads is 510 × 510 μm2 while the core area is 115 × 95 μm2. The total power consumption is 40.63 mW while the equalizer system consumes 11.18 mW under 1.2V power supply.