Level-based Buffer Insertion for Robust Clock Tree Synthesis
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 98 === As the manufacturing process in VLSI design technology continues to shrink, clock network synthesis nowadays considers not only keeping zero-skew property but also issues such as blockage handling, slew problems caused by long wires and process variation. Thus...
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| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78709604444332372702 |