| Summary: | 碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 98 === Briefly speaking, if a processor can process 1000 MIPS, it will provide which MIPS for us to operate Fast Fourier Transform (FFT). According to the MIPS it provides us, we can decide which N-points branch FFT of ASIC is suitable for us. FFT module is an indispensable part for wireless and mobile communication, especially when broadband wireless systems require a high speed and low power hardware module for its packet-based high-speed data transfer. This has made the design of FFT processor a critical requirement for the next generation wireless systems. In general, FFT module is designed for specific system. Therefore, it is desirable to design adaptive FFT module for different standards. This thesis adopts processor flexible characteristic and ASIC accelerated mechanism to set up a flexible FFT module which can meet IEEE 802.11n/16e standards. Besides, we propose optimized timing schedule for SISO/MIMO systems. After processor computational analysis, 64-points branch FFT of ASIC can be applied in proposed system and it computes 16-bits input data at a throughput rate of 85MHz. After that, we compare various pipeline-based FFT architectures suited to our system. Finally, it not only verifies the 8-points branch FFT on FPGA, but also checks proposed timing schedule which can satisfy IEEE 802.11n/16e specification.
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