Investigation on Board-Level and Chip-Level Charged-Device-Model ESD Issues in IC Products

• Main Authors: Huang, Chih-Kuo, 黃志國
• Other Authors: Ker, Ming-Dou
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/15371464758351379248

碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 98 === With the continuous evolution of semiconductor integrated circuit (IC) process, the device dimension growing narrow down and developing into nanoscale. Moreover, the transistors have been fabricated with thinner gate oxides to achieve higher speed or operation frequency due to the operation speed requirement of integrated circuits (ICs) in advanced process of complementary metal-oxide semiconductor (CMOS). In electrostatic discharge (ESD) events, the transistors are more easily damaged during ESD stress if they are fabricated with thinner gate oxides. The situation of gate oxide damage of transistors is a typical and familiar failure mechanism during chip-level charged-device-model (CDM) ESD test, especially in CMOS process. But in the applications of microelectronic system, IC chips must to be attached to the printed circuit board (PCB). The static charges will be stored in the PCB due to induction or rub and then deliver the charges to the IC chips through redistribution process during the attachment of IC chips to PCB. The instantaneous current flows into the IC chips is huge and will result in the damage of IC chips. It is the cause of board-level CDM ESD event. In the first part of this thesis, the focus is the investigation of characteristics and threats on board-level and chip-level CDM ESD in IC products. Furthermore, from the experimental results, the technique of failure analysis (FA) with fault isolation is applied to summarize the comparison of CDM failure mechanism caused by ESD event during CDM ESD test. The second part presents an experiment of ESD test between board-level and chip-level CDM on several samples fabricated with CMOS process. At first, the board-level CDM ESD current waveforms under different sizes of printed circuit boards (PCBs) and different charged voltage are measured. The experiment result has shown that the discharging current strongly depends on the PCB size and the charged voltage. Moreover, chip-level and board-level CDM ESD levels of several test devices and test circuits have been characterized and compared. Test results have shown that the board-level CDM ESD level of the test circuit is lower than the chip-level CDM ESD level, which demonstrates that the board-level CDM ESD event is more critical than the chip-level CDM ESD event. In addition, failure analysis reveals that the failure on the test circuit under the board-level CDM ESD test is much severer than that under the chip-level CDM ESD test. Based on the experiment results in this thesis, it is successfully proved that the failures caused by board-level CDM ESD event are more server than chip-level CDM ESD event and are easily mistaken for electrical over stress (EOS) related failures. Since the standard for the board-level CDM ESD test is not established so far, the experiment procedures in this thesis can be the reference for the establishment of the board-level CDM ESD test standard.