| Summary: | 博士 === 國立暨南國際大學 === 電機工程學系 === 98 === The aim of this thesis is to design the front-end circuits of CMOS receivers at the frequency of 24 GHz and 60 GHz, respectively. In the first half of this thesis, a low power 24-GHz low-noise amplifier (LNA), a 21-GHz CMOS receiver front-end, and a 24-GHz CMOS receiver front-end with differential I/Q output were implemented by TSMC 0.18-μm CMOS technology. In the later half of this thesis, a 55-GHz LNA, a 53.5 to 62-GHz wideband LNA, a V-band single-balanced mixer, and a 60-GHz receiver front-end were implemented by TSMC 0.13-μm CMOS technology.
First of all, the simulation result of the 24-GHz LNA shows that the power gain (S21) can be increased 44% (from 5.7 to 10.2 at 24 GHz) by adding a series peaking inductor to the input terminal in the third stage. The shunt RC feedback and a small series resistance Rd3 in the third stage were adopted to achieve excellent output impedance matching. The measured S21 and S22 are 10.03 dB and –35.6 dB at 24 GHz, respectively. In addition, the LNA only consumed 3.7 mW
Secondly, the 21-GHz CMOS receiver front-end consists of an LNA and a dual-gate mixer. At RF frequency of 24 GHz and IF frequency of 2.4 GHz, the measured conversion gain is 20.8 dB, the measured NF is and 8.6 dB. The power consumption is 43.2 mW.
A monolithic 24-GHz CMOS direct-conversion receiver is comprised of an LNA, two sub-harmonic mixers (SHMs), three miniature quadrature couplers (QCs), three miniature baluns, and two IF amplifiers. The SHMs in conjunction with the QCs and baluns are used to eliminate LO self-mixing. At RF frequency of 24 GHz and IF frequency of 100 MHz, the direct-conversion receiver dissipated 62.6 mW, the measured conversion gain is 31.8 dB.
The measured results show that the 55-GHz LNA achieves 8 dB S21 and 5.05 dB NF, gain and bandwidth of the 55-GHz LNA were not very satisfactory. A 53.5-62-GHz wideband LNA with six cascade common-source stages was designed for achieving sufficient the gain and bandwidth. The current-sharing technique in the second and the fourth stage was adopted for increasing the gain and bandwidth of the LNA. By this way, lower power consumption of wideband LNA could be achieved. To study the substrate loss affecting the performances of the LNA, the CMOS process compatible backside ICP (inductively coupled-plasma) deep trench technology was used to selectively remove the silicon underneath the LNA. Measured NF of 5.4~8.2 dB and 4.9~8 dB was achieved for the STD LNA and the ICP LNA, respectively, over the 54-63 GHz band.
The large output power and good phase noise is hard to achieve in a VCO at V-band. Both of the sub-harmonic mixers (SHMs) and active mixer with frequency doubler only need half of the LO frequency; hence we used active single-balanced mixer with frequency doubler to eliminate foregoing problems. The measured 3-dB bandwidth (W3dB) of V-band mixer is 9.5 GHz (48.5 to 58 GHz). The maximum conversion gain is 9.5 dB at 53 GHz while the consuming power is 31.5 mW.
Finally, the 60-GHz receiver front-end comprises a wideband LNA with 12.4 dB gain, a current-reused bleeding mixer, a baseband amplifier, and a 180o out-of-phase Wilkinson power divider. The receiver front-end consumed 50.2 mW and achieved input reflection coefficient at the RF port below 10 dB for frequencies from 52.3 to 62.3 GHz. The receiver front-end achieved maximum conversion gain of 18 dB at RF of 56 GHz. The corresponding 3-dB bandwidth (W3dB) of RF is 9.8 GHz (50.8 to 60.6 GHz).
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