| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 98 === With the evolution of process technology, the development of the integrated circuit has moved toward a high-density and high-integrated System-on-a-Chip (SoC). The clock generation and synchronization issues among different modules on SoC become more complex and important, and even turn into one of the bottlenecks in high performance systems.
In recent years, the Delay-locked loop (DLL) is used in system clock generators. Compared with conventional PLL-based system clock generators, DLL-based system clock generators exhibit less jitter and phase noise because of no jitter accumulation phenomenon in nature. According to the related research results, the DLL-based system clock generator is much more suitable for high-performance and/or high-speed SOCs to ensure the robustness of the entire system.
The cyclic delay line or edge combiner is adapted in conventional DLL-based system clock generators to achieve the function of programmable frequency multiplication. However, these circuits result in several problems listing as follows.
1. The clock signal cycles in delay-line loop causing jitter accumulation.
2. By selecting different input signal of multiplexer, the edge combiner can produce multiplied frequency output. Nevertheless, in feedback loop the latency of multiplexer causes the variations of duty-cycle and frequency of output clock.
In this thesis, a novel all-digital DLL-based frequency synthesizer (AD-DFS) was proposed. In the architecture design, digital to time-domain converter (DTC) and read-only memory (ROM) are used to replace the edge combiner in conventional DLL-based frequency synthesizer. With this novel architecture, several gains are shown below.
1. The multiplexer is no longer required in feedback path. Hence, the variations of output duty-cycle and frequency will become less.
2. Even the input clock duty-cycle is not 50%, the duty-cycle of the synthesized output clock will be very close to 50%.
3. By programming the content of read-only memory, arbitrary multiplication ratio can be realized. (In this thesis, the implemented multiplication ratios include 1x, 2x, 4/3x, 4x, 1/3x, 2/3x, and 1/2x)
4. The phase adjustment and tracking function are also merged into the architecture design, so that the output clock not only has a synthesized frequency but also in phase with input clock.
When designed with a 0.18 μm CMOS 1.8 V process technology, HSPICE simulation results show that the output frequency of the proposed AD-DFS ranges from 8.33 MHz to 2.6 GHz the output duty-cycle has an only 2% deviation. Besides, when the proposed AD-DFS operates from 400 MHz to 650 MHz, the static phase error between the input clock and output clock will be kept less than 19 ps. Furthermore, the maximal power consumption is 12.04 mW at output frequency 2.6 GHz.
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