| Summary: | 博士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This thesis presents a novel Algorithm/Architecture Co-exploration (AAC) design methodology that can concurrently explore both algorithms and architectures for the increasingly complex visual computing systems required for high-quality applications. Algorithmic complexity analysis and dataflow modeling at various granularities play significant roles in the presented concurrent optimization of both algorithms and architectures. To extract essential architectural information in early design stages and thus optimize the targeted architectures or platforms, the complexity measurements must be intrinsic. That is, they should be transparent to implementation details or design constraints and of course unbiased with regard to either hardware or software. This thesis introduces important intrinsic complexity measurements, including the number of operations, degree of parallelism, data transfer rate, and storage configuration. To accurately quantify the intrinsic algorithmic complexity, this thesis presents a systematic complexity analysis framework based on the eigen-decomposition of dataflow graphs at multiple granularities. The extracted complexity can reveal sufficient architectural information, enabling early back-annotation for modifying algorithms. In addition, this thesis also discusses the interplay among four complexity metrics, which significantly enlarges the architectural space. Several case studies based on the novel AAC methodology for electronic system level (ESL) design are also presented. Experimental results reveal that the introduced methodology can not only accurately characterize the algorithmic complexity but also facilitate the design space exploration of visual computing systems for generic platforms or architectures such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), reconfigurable architectures, and system-on-a-chip (SoC), single-processor, single instruction multiple data (SIMD), and multicore systems. Using the innovative AAC methodology, this thesis presents a better porting of the discrete wavelet transform onto SIMD; a high-quality, low-cost motion estimation ASIC; an efficient frame rate up-convertor on an FPGA; and a high-resolution de-interlacer on a low-cost consumer multicore platform for real-time visual computing applications. The significantly enhanced mapping of algorithms onto various platforms reveals the advantages and contributions of the presented design methodology.
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