Design and Implementation of Divide-by-three ILFD and Wide Tuning Range VCO for K-band Application

• Main Authors: Chih-YuLiu, 劉至祐
• Other Authors: Tzuen-Hsi Huang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/70437842553204189515

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === Due to the advances of market in consumer electronic products, many different standards and regulations of wireless communication system have been established. To fulfill the system requirements, the development of each individual RF circuit blocks for a special purpose is our design target in this thesis. In this work, we choose CMOS technology to implement the RF blocks such as frequency divider and oscillator due to its high integration capability and low cost. In this thesis, two divide-by-three injection-locked frequency dividers (ILFDs) within the frequency range of K-Band and a 22-29-GHz voltage-controlled oscillator (VCO) by using frequency tripling scheme have been proposed and characterized. The first work is an enhanced locking range divide-by-three ILFD with shunt-peaking and current-bleeding techniques. This work was fabricated in 0.18-μm CMOS 1P6M technology and it is operated in K-band. From the measurement results, the proposed circuit the total locking range is 3.86 GHz for an input injection power of 0 dBm. The power consumption is 4.28 mW at a supply voltage of 1.2V. The second- and third-order harmonic suppressions are 38.05 dBc and 37.89 dBc, respectively, for a divided output frequency of 8.4 GHz. The output phase noise under lock is -139 dBc/Hz at an offset of 1 MHz from the oscillation frequency as the input injection power is of +4 dBm. The second work is a 24-GHz quadrature divide-by-three injection-locked frequency divider with CMOS series-coupled topology. The quadrature outputs are generated by employing a modified topology which comes from a conventional CMOS series-coupled quadrature LC-oscillator with divide-by-three ILFD. This work was fabricated in 0.18-μm CMOS 1P6M technology, too. The measured locking range is 760 MHz for an injection power of 0 dBm. The second- and third-order harmonic suppressions are about 35.78 dBc and 39.37 dBc, respectively, for a divided output frequency of 7.72 GHz. The measured phase noises under lock are -119 dBc/Hz and -143.6 dBc/Hz at 100-KHz and 1-MHz offsets, respectively, with an injection power of +0 dBm. The last work is a 22-29-GHz wide tuning range oscillator by using the frequency tripling scheme from a VCO of 7~9 GHz. The proposed work has two stages which are composed of a low frequency generator and frequency tripler to attain the excellently wide frequency tuning capability. This work was also implemented by 0.18-μm CMOS 1P6M technology (now in chip fabrication). From the simulation results, tuning rage is 6.76 GHz and core dissipation power is 9.4 mW. The simulated phase noise is -104.2 dBc / Hz at 1 MHz offset frequency and figure-of-merit with tuning range (FOMT) is -191.4 dBc / Hz. The proposed work has achieved highest tuning range than previous published results.