| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === Pipelined analog-to-digital converters (ADCs) are generally regarded as the A/D converters with high-speed and medium-to-high-resolution characteristics, and they are widely adopted in wireless communication, video and digital-signal-processing (DSP) systems. Thanks to the evolution of the CMOS process, the channel length of MOS transistor is getting smaller, and its unit-gain transition frequency is getting higher. However, the lower supply voltage makes the op-amp design more difficult. In this thesis, we design and implement two high-speed and low-power pipelined ADCs with a 1.2-V supply voltage.
In the first work, a 10-bit 100-MS/s 1.2-V pipelined ADC has been carried out with TSMC standard 90-nm 1P9M CMOS process. This ADC adopts pseudo-differential class-AB telescopic cascode op-amp. Measurement results show that when the sampling frequency is 100 MS/s, the power consumption is 5.93 mW. The measured DNL and INL are within -0.44~0.46 LSB and -0.71~1.12 LSB at 100MS/s, respectively. The peak SNDR and SFDR are 54.71 and 68.6 dB at a 0.5-MHz input frequency, respectively. The ENOB is 8.8 bit. The ERBW is over 35 MHz. For higher sampling frequency, 150 MS/s, the peak SNDR and SFDR are 50.68 and 66.51 dB, respectively. The FOM of this ADC at 100 MS/s is 133 fJ/conversion-step. The chip area is 0.932mm2, and the active area is 0.235 mm2. The measured results demonstrate high power efficiency and high-speed potential of this ADC.
In the second work, a 12-bit 100-MS/s 1.2-V charge-pump-based pipelined ADC with foreground calibration has been proposed. It has been designed and implemented with TSMC standard 90-nm 1P9M CMOS process. The performance of a high-resolution pipelined ADC is mainly limited by the capacitor mismatch. Accordingly, we propose two charge-pump-based pipelined stages which are less sensitive to the capacitor mismatch, and the feedback factor of the 1.5-bit/stage MDAC is enhanced from 1/2 to 1. The foreground calibration, which is implemented in MATLAB, is used to correct the stage-gain error of pipelined stages. The measured results show that, with a 0.5-MHz sine wave and operating at 50 MS/s, the SNDR is 16.21 dB and 33.24 dB before and after calibration, respectively, and the power consumption is 13 mW. The chip area is 1.538 mm2, and the active area is 0.503 mm2.
|
|---|
