Performance Driven Level-Shifter Planning in Voltage Islands

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) has been widely applied to a real design to reduce dynamic-power consumption. However, to facilitate MSV, we have to insert level-shifters...

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Bibliographic Details
Main Authors: Zhi-XiongHung, 洪志雄
Other Authors: Jai-Ming Lin
Format: Others
Language:en_US
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/60993882213599913633
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Summary:碩士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) has been widely applied to a real design to reduce dynamic-power consumption. However, to facilitate MSV, we have to insert level-shifters for those signals across different voltage islands. The placement results of level-shifters have great impact on the area and wirelength for the resulting floorplan. There exists only one work considering this issue~cite{Yu09}, and, in their methodology, level-shifters are placed around the chip. However, to facilitate power planning for level-shifters, we have better to place level-shifters in a specified region, named level-shifter channels. In this paper, we propose a two-phase algorithm to deal with the level-shifters insertion problem. After level-shifterchannels have been allocated, we first roughly determine the positions of level-shifters by applying the network flow algorithm. Then, we use an integer linear programming (ILP) to determine the exact position of level-shifters in the second phase. The experimental results show that our algorithm can obtain better wirelength and area in a fast running time for level-shifter insertion.