Low-Cost Low-Power Cyclic and Pipelined Analog-to-Digital Conversion Techniques

• Main Authors: Chun-HsienKuo, 郭俊賢
• Other Authors: Tai-Haur Kuo
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/05645521976613236964

博士 === 國立成功大學 === 電機工程學系碩博士班 === 98 === This dissertation proposes two capacitor-swapping techniques, random feedback-capacitor interchanging (RFCI) and averaging RFCI (ARFCI) techniques, for cyclic analog-to-digital converters (ADCs) to reduce the harmonic distortion caused by capacitor mismatch. The RFCI technique improves upon the SFDR of conventional ADCs without sacrificing the SNDR. The ARFCI technique has better SNDR characteristics but less SFDR improvement than RFCI. The prior commutated feedback-capacitor switching (CFCS) technique can improve the SNR of ADCs. Therefore, this work proposes a reconfigurable cyclic ADC architecture that can be easily reconfigured to operate with one of the RFCI, ARFCI, and CFCS techniques by a simple timing control circuit. This reconfigurable topology provides three conversion characteristics with one item of intellectual property (IP) and thus greatly enhances the capabilities of cyclic ADCs. A leading-subcycles capacitor-error averaging (LCEA) scheme is also proposed to improve the flexibility of cyclic ADCs in the accuracy-speed tradeoff with simple structures. It can be used to enhance the figure of merit (FOM) of cyclic ADCs. A chip with 0.35um 2P4M 3.3V CMOS process is implemented and measured to demonstrate the proposed approaches. The chip size is 0.63 mm2. Measurement results show that the RFCI technique has about 7 dB and 0.5 dB higher SFDR and SNDR, respectively, than the conventional technique for the ADC. The ARFCI technique has about 10 dB and 6 dB higher SFDR and SNDR, respectively, than the conventional technique, while the conversion rate becomes 12/13 of that of the conventional technique. With the LCEA scheme, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional technique. This dissertation also proposes a bias-and-input interchanging (BII) technique that uses opamp summing node resetting (OSNR) to remove the memory effect of residue signals in cyclic/pipelined ADCs with opamp-sharing architectures. The proposed BII technique does not need an additional preamplifier stage or need to sacrifice signal swing, as do other OSNR techniques. Thus, the size of driving circuits and power consumption can be reduced. In the BII technique, fully differential (FD) and pseudo-differential (PD) BII opamp architectures are developed. Simple floating interconnection schemes are also proposed to eliminate the common-mode (CM) offset amplification for the PD architecture. 10-bit 80-MHz proof-of-concept ADCs with 0.18um 1.8V CMOS process confirm that the proposed BII technique can achieve OSNR more efficiently, using less power and achieving a wider signal swing than other OSNR techniques The FD-BII ADC shows a SNDR of 57.2 dB and a SFDR of 64.7 dB with an analog power of 20 mW. The PD-BII ADC shows a SNDR of 58.7 dB and a SFDR of 68.3 dB with an analog power of 14 mW. Finally, this dissertation proposes an averaging correlated double sampling (ACDS) technique to reduce the capacitor mismatch error and finite opamp gain error of cyclic/pipelined ADCs simultaneously. The ACDS technique produces complementary errors between two amplifying phases, so that the errors can be averaged. The ACDS technique can be combined with the opamp sharing architecture without adding more clock phases. With reduced sensitivities to capacitor mismatch and finite opamp gain, smaller sizes of capacitive loads and opamps can be designed, which lowers the cost and power consumption of ADCs. The combination of the ACDS and opamp sharing techniques can further save more cost and power. With the assigned opamp gain of 1000 and 0.4% capacitor mismatch, simulations results show that the ADC with the ACDS has 33.5 dB and 27.7 dB higher SFDR and SNDR, respectively, than the conventional ADC.