Design and Reliability Study of CMOS RF Power Cells

• Main Authors: Chien-HsuanLiu, 劉鍵炫
• Other Authors: Yan-Kuin Su
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/41868748394971565457

博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 98 === The radio-frequency (RF) power cells with high output power levels were designed by TSMC CMOS 0.18 μm 1P6M process. The power performances were measured at 5.2 GHz. The reliabilities were also measured and analyzed. The degradation from different stresses were discussed and compared with physical explanations. The design of the power cells of output power level of 10 dBm was the first step in the design procedure. Following is the designs of power cells with output power of 17, 20, and 23 dBm in turn. Based on the measurement results, the power amplifier of output power level of 23 dBm for 2.4 GHz was designed with the power cell with optimum power performances and reliabilities. The degradation from hot-carrier effect depended on input and output power levels, layout geometries, and load impedance mismatches. Two types of layout patterns were designed for the power cells of 10 and 17 dBm. The measurement results shows that the hot-carrier effect from RF reflected power by load impedance mismatch is much larger than that of DC stress at high bias voltages. The comparisons of degrees of degradation also indicate that the degradation is softened with dispersive layout structure under RF stress. From the comparison of degradation of power cells with output power levels of 10 and 17 dBm, it is found that the output power level of studied cells dominates the degradation both in DC and RF stress. The increased current and output power were equivalent to a higher electric field and current density at the drain terminal of MOSFET, and induced more serious hot-carrier effect and then more degradation. The detailed measurements and analyses of the load impedance mismatches are made with the power cells of output power level of 17 dBm. The influence of RF stress resulting from load impedance mismatches at the drain terminal on the device degradation has been quantified by the load mismatch factor, ML. Six different load impedances are chosen in order to study the dependence of degradation degree on the load impedance. The value of (1-ML) and the fundamental output power level dominate the amount of reflected power and the degree of degradation of drain current. The transient voltage and current swings at drain terminal also shows the same tendency. Another reliability issue of soft oxide breakdown in high power applications is also discussed. The effects of high RF power stress on drain current and power performances have been presented. Both the DC characteristics and power performances after hot-carrier effect and soft oxide breakdown were compared. From the experimental results of DC I-V curve, the threshold voltage shifted and the slope of drain current in the saturation region became much larger which was similar to the channel length modulation of MOSFET. The point of the pinch-off extended from drain terminal toward the source terminal and then the effective channel length was reduced in the stressed cell. The model of stressed power cells after soft oxide breakdown was introduced. Based on the measured results and performance comparisons in different layout patterns, it is observed that the geometry of the power cells with dispersive layout patterns has both better power performances and reliability. The power cells of output power of 20 and 23 dBm were designed by using the dispersive layout geometries. Otherwise, the problems of slots in the metal interconnects of current paths were solved for lower current density. The pre-match load-pull system is also used to help the measurement with smaller load impedance for power match. Finally, the power amplifier with output power level larger than 23 dBm at 2.4 GHz is designed.