| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 98 === Solid State Disks (SSDs) have been replacing the conventional magnetic storage devices in many consumer electronic systems. One of the main advantages of SSDs is their parallel architecture consist of multiple flash chips, planes and internal buses. Unlike traditional flash translation layers for single flash memory chip, the FTL for a SSD must utilize the concurrency of the multiple chips and buses as possible.
Log-buffer based flash translation layer (Hybrid mapping FTL) is widely employed on low-end and even middle-end solid-state drives (SSDs) which equip insufficient on-board memory. Although adopting hybrid mapping FTL on SSDs can release much memory space for buffer cache than that used by page-level mapping FTL, its cleaning cost may be much higher due to cross-chip live page copy and inter-plane live page copy while chasing parallelism. To address the problems, in this paper, we suggested an update page placement policy (log-block allocation policy) and a software layer cooperation mechanism between FTL and buffer management to maximize the degree of parallelism while alleviating the cleaning cost at the same time. We run trace-driven simulations to verify our design and the simulation shows that it improved the requests response time up to about 5 times compared to existing policies and reduced the cleaning cost significantly.
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