DESIGN OF A NOVEL FLASH TRANSLATION LAYER WITH EFFICIENT UTILIZATION OF SPARE AREA FOR NAND FLASH MEMORY

• Main Authors: Pei-Kuan Lin, 林倍寬
• Other Authors: Da-Wei Chang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/07338902557802990975

碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 98 === In NAND flash-based storage systems, a flash translation layer (FTL) is employed to hide the erase-before-write characteristics of NAND flash memory. Among several efficient FTLs, Superblock FTL achieves good performance in consideration of garbage collection (GC) overhead, space utilization and memory usage. It combines multiple adjacent logical blocks into a superblock which is mapped at coarse granularity, while the pages inside one superblock are mapped freely at fine granularity to any location in several physical blocks. The fine-grained mapping information is stored in the spare area of NAND flash memory for reducing memory usage. However, the restricted space of spare area limits the size of a superblock and thus reduces the benefits of Superblock FTL. In this thesis, we propose ESB (Extended Superblock) FTL inheriting from the Superblock FTL. ESB keeps the advantage while eliminates the limitation of the Superblock FTL. This is achieved by dividing the mapping of a logical block into multiple groups, assigning different roles to spare areas, and storing different types of mapping information in the spare areas with different roles. The design of ESB allows it to support large superblocks, reducing the garbage collection overhead further. The simulation results on five traces show that the ESB FTL decreases the garbage collection overhead by up to 947%, compared to Superblock FTL. In addition, ESB achieves better performance in aspects of space utilization and response time