| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 98 === In recent years, integrated circuit technology becomes more sophisticated, so more and more portable electronic products appear in our daily lives. The portable products require small sizes, nice looking, and multi-functions. Therefore, integrated circuits tend to very low power consumption.
In applications of the reference voltage circuits, many circuits such as: D/A, A/D converters, voltage regulators, etc., require a reference voltage circuit to provide the accurate reference voltage effectively. In this paper, we propose a low-voltage, low-power pure CMOS voltage reference circuit on very small area with temperature drift calibration. This circuit was fabricated on area of 0.0076mm2 using TSMC 0.18μm CMOS process. The measurement results reveal that the power consumption is 74nW, with temperature coefficient of 6.7ppm/oC after calibration.
The conventional LDO voltage regulators require a large external capacitor (a few μF) in order to maintain stability due to negative feedback. However, in the integrated circuits, even the nF capacitor occupies very large chip area, which is not cost effective. Another goal in this thesis is to design a linear regulator without external capacitors (cap-free LDO). The LDO utilizes a three-stage amplifier with nested Miller compensation. The circuit may be equivalent to a single pole circuit for stability. The proposed circuit was designed using TSMC 0.35μm CMOS process for the maximum load current of 150mA. The simulation results show that input voltages are 2.8V ~ 5V and 3.3V ~ 5V for the output voltage of 2.5V and 3.3V, respectively. The dropout voltage is 300mV, and the quiescent current is 96μA. For the worst case without external capacitors, the undershoot voltage is 220mV and the overshoot voltage is 206mV.
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