Test Interface and Integration for High Yield 3D IC Design

Test Interface and Integration for High Yield 3D IC Design

碩士 === 國立中興大學 === 資訊科學與工程學系所 === 98 ===

Bibliographic Details
Main Authors: Ming-Hsien Wu, 鄔明憲
Other Authors: Sying-Jyan Wang
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/91212449306150110345
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spelling ndltd-TW-098NCHU53940762015-10-30T04:05:20Z http://ndltd.ncl.edu.tw/handle/91212449306150110345 Test Interface and Integration for High Yield 3D IC Design 可提升三維晶片良率之測試介面整合設計 Ming-Hsien Wu 鄔明憲 碩士 國立中興大學 資訊科學與工程學系所 98 Sying-Jyan Wang 王行健 2010 學位論文 ; thesis 47 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立中興大學 === 資訊科學與工程學系所 === 98 ===
author2 Sying-Jyan Wang
author_facet Sying-Jyan Wang
Ming-Hsien Wu
鄔明憲
author Ming-Hsien Wu
鄔明憲
spellingShingle Ming-Hsien Wu
鄔明憲
Test Interface and Integration for High Yield 3D IC Design
author_sort Ming-Hsien Wu
title Test Interface and Integration for High Yield 3D IC Design
title_short Test Interface and Integration for High Yield 3D IC Design
title_full Test Interface and Integration for High Yield 3D IC Design
title_fullStr Test Interface and Integration for High Yield 3D IC Design
title_full_unstemmed Test Interface and Integration for High Yield 3D IC Design
title_sort test interface and integration for high yield 3d ic design
publishDate 2010
url http://ndltd.ncl.edu.tw/handle/91212449306150110345
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AT wūmíngxiàn testinterfaceandintegrationforhighyield3dicdesign
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AT wūmíngxiàn kětíshēngsānwéijīngpiànliánglǜzhīcèshìjièmiànzhěnghéshèjì
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