A Redundant Fault Tolerant Method by Using CVSL Logic
碩士 === 國立中興大學 === 資訊科學與工程學系所 === 98 === For the deep sub-nanometer manufacturing process, the fault tolerant processing issue has been becoming more and more important than before. There are a number of technologies have been propose to improve the process yield by using many other different metho...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61618109521513474911 |
| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系所 === 98 === For the deep sub-nanometer manufacturing process, the fault tolerant processing issue has been becoming more and more important than before. There are a number of technologies have been propose to improve the process yield by using many other different methods. To solve this issue, our paper is to propose a method of using CVSL architecture as a basis to design circuit with fault tolerant capability. Our method can be applied to a variety application of logic. In our paper, we adopt the test mode to detect the open fault. We also propose an isolate mode to ensure the circuit can be work normally after the faulty circuit has been detect. In our research we have to issue that the the usage Pseudo nMOS logic has to satisfy the requirements of minimum complexity and minimal power consumption.
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