| Summary: | 碩士 === 國立中興大學 === 光電工程研究所 === 98 === A cyclic digital-to-analog converter (CDAC) which adopts serial input signal has a simple structure and can convert arbitrary bits. However, its conversion time increases with the increasing input bits. In previous studies, one has presented that the double-conversion-rate CDAC, which uses four capacitors can input the most-significant bit (MSB) and the least-significant bit simultaneously. However, the capacitor area of the double-conversion-rate CDAC is doubled as compared to the traditional one.
This paper presents an improved double-conversion-rate CDAC, which contains only three capacitors. The proposed circuit can sample input data and share charges at the same phase clock, so its conversion rate is also about two times of the traditional CDAC. Comparing with double-conversion-rate CDAC, The proposed circuit needs fewer capacitors and adopts capacitor swapping technique, thereby reducing chip area and improving nonlinearity errors of the DAC. Simulation results show that under the condition of 0.1% of capacitive mismatching, the nonlinearity error of the proposed CDAC with capacitor swapping is reduced to below one-tenth of that without capacitor swapping
The proposed CDAC is designed using a TSMC 0.35 μm CMOS technology with a power supply of 3.3V. The post-simulation results show that the maximum INL and DNL of the CDAC with capacitor swapping are 0.76 and 0.8 LSB, respectively. They conform to the specification of 1 LSB.
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