Simulation Based Investigation to Reduce Production Cycle Time for Wafer Fabrication

• Main Authors: Tsung-Shiun Hsieh, 葉宗訓
• Other Authors: Ping-Yu Chang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/39624260277740876346

碩士 === 明志科技大學 === 工業工程與管理研究所 === 98 === In recent years, with the huge capital investments and high level of market competitiveness, semiconductor manufacturing industries must innovate of new process technology to increase market share and profit. Cycle time reduction is proved to increase productivity, product reliability, and product quality in wafer manufacturing. Hence, this study of wafer manufacturing was focus on cycle time reduction. There are five different kinds of products in the wafer simulation model. This simulation model also contains three factors, that is amount of feeding material、dispatching rule and number of machines. The influence of cycle time reduction in the different factor combination is compared and discussed in this research. Furthermore, four levels of dispatching rules, two levels of feeding material, and two levels of number of machines are conducted in this research. The result shows that the factor combination with the most significant effect on cycle time reduction is 600 chips per day, Due Date Quoting dispatching rule, and adding one machine to photo workstation. However, according to the analysis of adding one machine will have more cost and could not achieve break-even in appropriate time. Therefore, cycle time reduction should be achieved using Due Date Quoting and 600 chips per day without adding any machine under financial analysis.