| Summary: | 碩士 === 明新科技大學 === 系統晶片與嵌入式系統產業研發研究所 === 98 === With the progress of science and technology industry, not off, consumer demands for electronic products, in order to meet consumer demand, IC design companies to develop a variety of products to meet market trends, multi-system towards integrated chip (SOC ; System on a Chip) development, so that the product may have more multi-functional external and has a superior performance.
In the current IC Packaging domain, process most of the use of gold wire connected chips and substrates, but gold prices have been skyrocketing in recent years, resulting in the cost of increasing on packaging. It can reduce the cost about 10 ~ 20% to replac the gold wire into copper wire.
This study is intended for 20 um palladium plated copper wire with mature in the mass production of 20 um gold wire of LQFP ( Low Profile Quad Flat Package ) 128 pin package, through the three stages of the experiments and comparisons, to identify key parameter combinations by BIT ( Bonding Integration Testing ), MIT (Molding Integrated Test) and reliability testing to analysis the quality characteristics of palladium plated copper wire.
Learned from the experimental results, the key parameters setting can be assured of the best in the quality characteristics. At the same time on workability do more than on, found in more longer process time, production control more stringent, but yield and quality is same to gold, costs can be reduced about 10 ~ 20%.
Different from the past validation rules, the copper wire problems with easy-to-oxidation, and hardness is too high, easily damage to the pad, and other considerations. Packages should be qualified by each product material structure, especially in the advanced wafer technology.
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