The Design of Double Cross-Coupled VCO/QVCO and High Conversion-gain Mixer

• Main Authors: Tung-Fu Yu, 余同釜
• Other Authors: Jen-Chun Fang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/31530327783220788627

碩士 === 龍華科技大學 === 電子工程研究所 === 98 === This thesis presents the designing of integrated circuit radio frequency voltage controlled oscillators and Mixer. The VCO is used CMOS cross coupled structure, it adopted double cross couple technique to improve power consumption and phase noise since have good performance, so make use of this VCO again to design a Quadrature VCO with series coupled. The mixer was designed with Gilbert Cell structure, the design toward high conversion-gain and high linear, design two mixer IC respectively, one of the mixer design adopeted current-bleeding technique and used inverter designs work at 5.4GHz high conversion-gain down-conversion mixer, the other one adopeted cross coupled in RF stage and apply inductor couple parasitic capacitance in LO stage achieves high conversion-gain high linear and low power consumption down-converison mixer. There four IC are simulation by ADS and chip fabrication by TSMC 0.18-μm 1P6M CMOS technique. The first chip is “High-performance Low Power Consumption Cascode Double Cross Couple VCO For WIMAX” The design utilizes cascode structure with double cross couple circuit to reduce phase noise and power consumption, while also utilizing two MOS Variable capacity switched capacitances to increase tuning range achive batter performance . The VCO power consumption 1.32mW from 1.3V power supply and the oscillation frequency is 5.6 GHz. The phase noise is -118.8dBc/Hz at 1MHz offset from the carrier frequency. Tuning range is 900MHz. The figure of merit is -192.4 and the chip area is 0.65 x 0.65 mm2. The second chip is “A High-performance Low-phase noise QVCO with Cascode Double Cross-couple Circuit” The design utilizes two Cascode CMOS VCO with double cross couple circuit that uses serise coupled technique to generate a quadrature signal. The QVCO power consumption 8.4 mW from a 1.8 V power supply and oscillation frequency is 5.59 GHz. The phase noise is -119.8dBc/Hz at 1MHz offset from the carrier frequency,The Figure of merit is -185 and the chip area is 1 x 0.65 mm2. The third chip is “Down-conversion Mixer With Conversion-gain Enhancement Schematic Operated in 5.4GH ” The design utilizes conventions Gilbert cell with inverter and current bleeding technique achive high conversion-gain. The MIXER power consumption 11.2 mW from a 1.5 V power supply and RF frequency is 5.4 GHz, LO frequency is 5.3GHz The output IF frequency is 100MHz, conversion-gain is 11.5dB, linear is -6dBm P1dB is -12dBm, noise is 13.7dB(SSB) and the chip area is 1.14x 0.775 mm2. The fourth chip is “Low Power-consumption High Conversion-gain Down-conversion Mixer For WIMAX” The design utilizes inductor couple parasitic capacitance improve noise and linear, IF output adopted active load raised conversion-gain and reduce power consumption. The MIXER power consumption 2.68 mW from a 1.5 V power supply and RF frequency is 6 GHz, LO frequency is 5.9GHz The output IF frequency is 100MHz, conversion-gain is 21.9dB, linear is -9.2dBm P1dB is -20.4dBm, noise is 10dB(SSB) and the chip area is 0.94x 0.75 mm2.