A Study of the Optimization of the Forming Stress of the IC Outer Leads for Semiconductor Packaging

• Main Authors: Liang-Ku Shen, 沈亮谷
• Other Authors: Chao-Ho Hsu
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/16789468888019272807

碩士 === 國立高雄應用科技大學 === 模具工程系 === 98 === In recent years, the environmental production process was introduced into the semiconductor packaging industry. Alternatively, all its materials were environmental. The new process conditions and parameters resulted from the new environmental materials, the consideration for the cost of the new environmental materials, and the stricter failure determination criterion of J-STD. make the products by the new environmental production process, fail to meet the J-STD. specifications for pin delamination and cracks and thus be rejected by the clients. In this study, DEFORM-3D, the analysis software, was applied to simulate and analyze the IC elements. To find the optimal residual stress for bending forming and thus help to improve the problems encountered by the semiconductor packaging industry, the angle of the punch during preforming and the way of preforming as well as the punch arc (R) size and the way of bending forming were explored, given the distribution of the stress and strain taken by the IC outer leads that were being pre-formed and bent and formed. In this study, it was found that the optimal stress value for the one-side impact pressure for the preforming of the IC outer leads was 45 degrees and that for the two-side simultaneous impact pressure was 40 degrees. With respect to the stress for bending forming, the optimal size of the form punch arc (R) was 0.5 mm. Also, it was found that the stress value was better while there was a design of preforming and rebending forming than that while there was a design of direct bending forming. This study could be a reference for the IC packaging industry to design the tools for the IC outer leads. To deduct the selection trials of the packaging materials and the try runs of the process parameters, decrease the alternations of the modifications of the form tools, and thus make the IC elements soon pass the reliability certification, it is feasible to minimize the stress taken by the IC elements while the outer leads are formed.