Pipeline Fast Fourier Transform Processors Realization with Various Complex Multipliers

• Main Authors: Chong-Chou Wu, 吳忠洲
• Other Authors: Hung-Yu Wang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/60415564356231341991

碩士 === 國立高雄應用科技大學 === 電子工程系 === 98 === Due to the popularity of the communication systems, the Fourier transform is still one of research and development topics of wired and wireless communication. The high-speed computing of the discrete Fourier transform is very important in the real-time signal processing system. So many fast Fourier transform (FFT) algorithm are developed. Because of the regularity of FFT algorithm, it is very suitable for the implementation by using hardware circuits. Most of the developed algorithms reduce the computational complexity. In this thesis, we use radix-22 algorithm which can reduce the computational complexity from to . In this study, we compare various circuit architectures of fast Fourier transform in the view of hardware regularity, needed memory space and the number of computing operation. Finally, we adopt the radix-22 algorithm and the single-path delay feedback (SDF) architecture to implement the high-performance FFT processor. The conventional complex multiplier, multiplier-less canonical signed digit (CSD) complex multiplier and coordinate rotation digital computer (Cordic) architecture are used to realize pipelined fast Fourier transform processors. To reduce the error, we also realize our complex multiplier computing circuits with the double rounding technique. The Xilinx ISE software is used to synthesis the hardware, it shows that the 16-point FFT processor based on the multiplier-less canonical signed digit (CSD) complex multiplier can achieve the advantages of less needed hardware and moderate accuracy.