A Study of VCO & PLL Based on Active Load Differential Amplifiers

碩士 === 崑山科技大學 === 電子工程研究所 === 98 === In this thesis, we use the differential amplifier with high input impedance, high output impedance and high voltage gain characteristics, to implement a differential amplifier voltage controlled oscillator ( VCO ),and can be applied on PLL circuit design. The dif...

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Main Authors: Chia-Hsiang Chang, 張家祥
Other Authors: Cher-Shiung Tsai
Format: Others
Language:zh-TW
Published: 2010
Online Access:http://ndltd.ncl.edu.tw/handle/59760195659586913021
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spelling ndltd-TW-098KSUT54280152015-10-13T19:07:19Z http://ndltd.ncl.edu.tw/handle/59760195659586913021 A Study of VCO & PLL Based on Active Load Differential Amplifiers 以主動負載差動放大器為基礎的壓控振盪器與鎖相迴路之研究 Chia-Hsiang Chang 張家祥 碩士 崑山科技大學 電子工程研究所 98 In this thesis, we use the differential amplifier with high input impedance, high output impedance and high voltage gain characteristics, to implement a differential amplifier voltage controlled oscillator ( VCO ),and can be applied on PLL circuit design. The differential amplifier voltage controlled oscillator ( VCO ) base on the framework of differential amplifier, to design CMOS and BiCMOS differential amplifier voltage controlled oscillators. In the Phase-Locked Loop ( PLL ) circuit takes active load differential amplifier oscillator as main core to design CMOS active load differential amplifier oscillator. This circuit is simulated and verified by Advanced Design System (ADS), with tsmc 0.35-μm BiCMOS technology for the differential amplifier Ring VCO, and tsmc 0.18-μm CMOS technology for the active load PLL. Key performance:the VCO has a wide operating frequency range, from 399 MHz to 4134 MHz with 0.7 V to 1.8 V supply voltage, The PLL lock frequency is 2880 MHz, and lock time is under 4 μs, and total power consumption is 7.398 mW and the output power is 10.707 dBm. The complete PLL including its on-chip loop filter occupies 623×623 μm2. Cher-Shiung Tsai 蔡澈雄 2010 學位論文 ; thesis 68 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 崑山科技大學 === 電子工程研究所 === 98 === In this thesis, we use the differential amplifier with high input impedance, high output impedance and high voltage gain characteristics, to implement a differential amplifier voltage controlled oscillator ( VCO ),and can be applied on PLL circuit design. The differential amplifier voltage controlled oscillator ( VCO ) base on the framework of differential amplifier, to design CMOS and BiCMOS differential amplifier voltage controlled oscillators. In the Phase-Locked Loop ( PLL ) circuit takes active load differential amplifier oscillator as main core to design CMOS active load differential amplifier oscillator. This circuit is simulated and verified by Advanced Design System (ADS), with tsmc 0.35-μm BiCMOS technology for the differential amplifier Ring VCO, and tsmc 0.18-μm CMOS technology for the active load PLL. Key performance:the VCO has a wide operating frequency range, from 399 MHz to 4134 MHz with 0.7 V to 1.8 V supply voltage, The PLL lock frequency is 2880 MHz, and lock time is under 4 μs, and total power consumption is 7.398 mW and the output power is 10.707 dBm. The complete PLL including its on-chip loop filter occupies 623×623 μm2.
author2 Cher-Shiung Tsai
author_facet Cher-Shiung Tsai
Chia-Hsiang Chang
張家祥
author Chia-Hsiang Chang
張家祥
spellingShingle Chia-Hsiang Chang
張家祥
A Study of VCO & PLL Based on Active Load Differential Amplifiers
author_sort Chia-Hsiang Chang
title A Study of VCO & PLL Based on Active Load Differential Amplifiers
title_short A Study of VCO & PLL Based on Active Load Differential Amplifiers
title_full A Study of VCO & PLL Based on Active Load Differential Amplifiers
title_fullStr A Study of VCO & PLL Based on Active Load Differential Amplifiers
title_full_unstemmed A Study of VCO & PLL Based on Active Load Differential Amplifiers
title_sort study of vco & pll based on active load differential amplifiers
publishDate 2010
url http://ndltd.ncl.edu.tw/handle/59760195659586913021
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