Design of Pipelined Multiprocessor System-on-a-Chip and Application in Real-Time Fingerprint Recognition

• Main Authors: Jia-Hong Dai, 戴嘉宏
• Other Authors: Yuan-Wei Tseng
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/34830306064464257075

博士 === 義守大學 === 電機工程學系博士班 === 98 === In this dissertation, we propose a methodology for complex computing system design and rapid hardware synthesis. It provides a systematic and high efficient design flow to assist the designer realize hardware circuit synthesis of system rapidly. We planned a Pipelined Multiprocessor System-on-a-Chip (PMPSoC) design flow. The PMPSoC design flow consists of decomposition of algorithm, data arrangement, pipelined controller design, HW/SW co-simulation and HW/SW co-synthesis. For the complex system, we can divide it into several individual and independent modules. Each independent module function is completed by software in the embedded processor. When applying the pipelining technology to synthesize the hardware of main controller to integrate all modules, the totally system performance is increased. We completed a simulator of pipelined multiprocessor system. The contribution is (1) the simulation level is raised from register transfer level (RTL) to transaction-level model (TLM) that can greatly reduce the time taken for system verification; (2) after the system architecture is decided, the simulator can generate a simulation platform of pipelined multiprocessor system automatically. We can validate the functions of the pipelined multiprocessor system before committing to physical hardware implementations and realize the objective of rapid prototyping. We apply the PMPSoC design flow to the SoC for fingerprint person authentication application. In this dissertation, we introduce a minutia-base and a low complexity fingerprint recognition algorithm. Finally, we use minutiae-base fingerprint recognition algorithm in PMPSoC design. In the process of HW/SW co-simulation, we showed PMPSoC simulator can generate a pipelined multiprocessor simulation platform immediately according to the configuration of multiprocessor system architecture. We load the program code of the multiprocessor to execute the HW/SW co-simulation of TLM layer and validate the system functions and evaluated the execution time of each module in system. In the same frequency of system clock, the performance of fingerprint recognition on the PMPSoC achieves a speedup of 455.1% than on single processor, the memory can be reduced 32.53%, and lower power consumption. The experimental result shows that the PMPSoC design methodology is valuable for embedded systems applications.