Design and Implementation of an Effective Built-In Self-Test Scheme for Parallel Multipliers
碩士 === 輔仁大學 === 電子工程學系 === 98 === Efficient built-in self-test techniques are proposed [3] and implemented for parallel multipliers. Efficient test patterns are generated for fault detection of the target multipliers (including carry-save multiplier and Wallace tree multiplier). Therefore, defect le...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/18070531300570142112 |