Design and Implementation of an Effective Built-In Self-Test Scheme for Parallel Multipliers

• Main Authors: Chen, Ching-Huan, 陳清環
• Other Authors: Kuan-Jen Lin, Ph.D., Shyue-Kung Lu, Ph.D.
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/18070531300570142112

碩士 === 輔仁大學 === 電子工程學系 === 98 === Efficient built-in self-test techniques are proposed [3] and implemented for parallel multipliers. Efficient test patterns are generated for fault detection of the target multipliers (including carry-save multiplier and Wallace tree multiplier). Therefore, defect level can be reduced significantly. We adopt the cell fault model which is widely used in the area of systolic array testing. The test pattern generator of the BIST architecture is a linear feedback shift register (LFSR) or an 8-bit binary counter; moreover. The output response analyzer is an accumulator with rotate-carry adder. The number of test patterns is 256 and the hardware overhead is about 3.9 % for implementation of an 16-bit Wallace Tree multiplier with BIST structures added. According to experimental results, the fault coverage can achieve up to 99 %.