Design and Implementation of AES Algorithm with Modes of Operation on SOPC Platform

• Main Authors: Ching Hung Jhan, 詹清宏
• Other Authors: Kuan Jen Lin
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/55715222913920420374

碩士 === 輔仁大學 === 電子工程學系 === 98 === The AES encryption/decryption algorithm is widely used in modern consumer electronic products for security. The algorithm can be run with multiple modes of operation, including ECB, CBC, OFB and CTR modes. In this thesis, we design an all-in-one circuit that supports all modes of operations. The design was implemented using an SOPC platform, DE2. The proposed architecture and circuits are suitable for FPGA realization. Furthermore, two different methods were used to implement the interface to CPU Nios II: custom instruction and avalon memory-mapping. The comparison in terms of area and speed will be shown in experimental results.