| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 98 === With the progress of VLSI technologies and the trend of the system integration, the scale of circuits in the future will have more transistors in the same chip, which implies that systems can be embedded on a single chip compared with many chips on a board in the pase. With the system integration concept the mechanism of built-in power management is therefore highly desired.
In this thesis, we propose a mechanism of multiple-access for dc-dc buck conversion to reduce large amount of memory for fully table look-up. Moreover, we also enhance the architecture of hybrid DPWM to reduce the number of behavior error. The proposed regulator controller employs comparators with the hysteresis characteristic, a error process unit (EPU) for 1-bit voltage correction, a multiple-access PID compensator and a low-power digital PWM (DPWM). Based on
the multiple-access mechanism, the proposed controller can alleviate the penalty of large amount of memory employed for fully table look-up based PID compensator in the application of power regulation.
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