Testable and BIST Architectures for Motion Estimation Computing Arrays

• Main Authors: Chen-Yuen Huang, 黃俊源
• Other Authors: Shyue-Kung Lu
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/71851307933368570083

碩士 === 輔仁大學 === 電子工程學系 === 98 === Motion estimation is the main computation used in video coding systems. It’s the most computation-intensive part. Because of the simplicity and regularity, the block matching algorithms are widely used for the computation of motion vectors. With the advance of VLSI technology, integration of the motion estimation computing array into a single chip or a system-on-chip (SOC) design is becoming possible. However, integrating a large number of processing elements (PEs) on a single chip or SOC will increase the logic-per-pin ratio, which drastically reduces the efficiency of testing the logic on the chip. In order to deal with these problems, design-for-testability and BIST techniques are proposed for motion estimation computing arrays. The bit-level or word-level cells (modules) in the array are made bijective to meet the C-testability conditions. The test pattern generator can be a simple binary and the output response analyzer is basically a checksum comparator. The number of test patterns is 32 and 2w for the bit-level and module-level designs, respectively. The hardware overhead of the BISTed motion estimation array is only 2 %. In order to tradeoff between the hardware overhead and the number of test patterns, a scalable DFT technique was also proposed in this thesis.