Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB
碩士 === 逢甲大學 === 通訊工程所 === 98 === This thesis circuits are divided into four parts, and it is applied to the 13 GHz in the chapter 4 to the chapter 6. And it is applied in the satellite communications. The first part is the chapter 4, the circuit design is applied cascode structure. The second part i...
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ndltd-TW-098FCU056500122016-04-20T04:18:19Z http://ndltd.ncl.edu.tw/handle/80271620697478888920 Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB 利用CMOS0.18製程之13GHz與超寬頻的低雜訊放大器電路設計與製作 Tseng-Hsun Yuan 袁贈勛 碩士 逢甲大學 通訊工程所 98 This thesis circuits are divided into four parts, and it is applied to the 13 GHz in the chapter 4 to the chapter 6. And it is applied in the satellite communications. The first part is the chapter 4, the circuit design is applied cascode structure. The second part is the chapter 5, the circuit design is applied cascade structure. The third part is the chapter 6, it designs a variable gain LNA (Low Noise Amplifier). The fourth part is the chapter 7 and designs an Ultra Wide Band (UWB) system. This thesis, from the design flow, circuit simulation, layout of the circuit, and the circuit measurement are based on the TSMC 0.18 μm standard. For the first circuit design was applied 13 GHz. The main structure is the cascode and the cascode can restrain the miller effect. It used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -32 dB; the output return loss (S22) is -5.2 dB; the power gain (S21) is 9.9 dB; the isolation (S12) is -32.616 dB; the NF (noise figure) is 5.5 dB; unconditional stability; the P1dB is -12 dBm. Modification of the LNA, for the simulated results, the input return loss (S11) is -21.938 dB; the output return loss (S22) is -19.075 dB; the power gain (S21) is 14.89 dB; the isolation (S12) is -32.737 dB; the NF is 3.059 dB; unconditional stability; the P1dB is -12 dBm. The second circuit was design for 13 GHz application, the main structure is the cascade. It used the cascode structure at the three-stage, and it can restrain the miller effect. It used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -15.45 dB. The output return loss (S22) is -9.47 dB; the power gain (S21) is 9.34 dB; the isolation (S12) is -30.364 dB; the NF (noise figure) is 4.76 dB; unconditional stability; the P1dB is -13 dBm. The third part was applied for the 13 GHz, the main structure is the cascade and cascode. It used a cascode current mirror at the four-stage, and it can inhibit the channel length modulation effect. It used the diode to raise the P1dB and it used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -12.595 dB; the output return loss (S22) is -11.98 dB; the power gain (S21) is 9.4 dB; the isolation (S12) is -27.91 dB; the NF (noise figure) is 4.3 dB; unconditional stability; the P1dB is -9.9 dBm. The fourth part is the UWB LNA. The main schematic is the three stages cascade and it can raise the bandwidth and gain. At the first stage, we used the feedback network for raise the flatness and used the inter stage inductor for restrain the miller effect. At the frequency of the 3.1~10.6 GHz and the measured results, the input return loss (S11) is -35.0657 dB; the output return loss (S22) is -12.3755 dB; the power gain (S21) is 17.7427 dB; the isolation (S12) is -44.7844 dB; the NF is 3.64 dB; unconditional stability; the P1dB is -26 dBm @ 6.1 GHz. Modification of the LNA, for the simulated, the input return loss (S11) is -13.752 dB; the output return loss (S22) is -12.207 dB; the power gain (S21) is 16.246 dB; the isolation (S12) is -54.828 dB; the NF is 3.675 dB; unconditional stability; the P1dB is -26 dBm @ 6.1 GHz. Man-Long Her 何滿龍 2010 學位論文 ; thesis 140 en_US |
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碩士 === 逢甲大學 === 通訊工程所 === 98 === This thesis circuits are divided into four parts, and it is applied to the 13 GHz in the chapter 4 to the chapter 6. And it is applied in the satellite communications. The first part is the chapter 4, the circuit design is applied cascode structure. The second part is the chapter 5, the circuit design is applied cascade structure. The third part is the chapter 6, it designs a variable gain LNA (Low Noise Amplifier). The fourth part is the chapter 7 and designs an Ultra Wide Band (UWB) system.
This thesis, from the design flow, circuit simulation, layout of the circuit, and the circuit measurement are based on the TSMC 0.18 μm standard. For the first circuit design was applied 13 GHz. The main structure is the cascode and the cascode can restrain the miller effect. It used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -32 dB; the output return loss (S22) is -5.2 dB; the power gain (S21) is 9.9 dB; the isolation (S12) is -32.616 dB; the NF (noise figure) is 5.5 dB; unconditional stability; the P1dB is -12 dBm. Modification of the LNA, for the simulated results, the input return loss (S11) is -21.938 dB; the output return loss (S22) is -19.075 dB; the power gain (S21) is 14.89 dB; the isolation (S12) is -32.737 dB; the NF is 3.059 dB; unconditional stability; the P1dB is -12 dBm.
The second circuit was design for 13 GHz application, the main structure is the cascade. It used the cascode structure at the three-stage, and it can restrain the miller effect. It used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -15.45 dB.
The output return loss (S22) is -9.47 dB; the power gain (S21) is 9.34 dB; the isolation (S12) is -30.364 dB; the NF (noise figure) is 4.76 dB; unconditional stability; the P1dB is -13 dBm.
The third part was applied for the 13 GHz, the main structure is the cascade and cascode. It used a cascode current mirror at the four-stage, and it can inhibit the channel length modulation effect. It used the diode to raise the P1dB and it used the source degeneration for stabilization of the inductor. Operating of the 13 GHz and the measured results, the input return loss (S11) is -12.595 dB; the output return loss (S22) is -11.98 dB; the power gain (S21) is 9.4 dB; the isolation (S12) is -27.91 dB; the NF (noise figure) is 4.3 dB; unconditional stability; the P1dB is -9.9 dBm.
The fourth part is the UWB LNA. The main schematic is the three stages cascade and it can raise the bandwidth and gain. At the first stage, we used the feedback network for raise the flatness and used the inter stage inductor for restrain the miller effect. At the frequency of the 3.1~10.6 GHz and the measured results, the input return loss (S11) is -35.0657 dB; the output return loss (S22) is -12.3755 dB; the power gain (S21) is 17.7427 dB; the isolation (S12) is -44.7844 dB; the NF is 3.64 dB; unconditional stability; the P1dB is -26 dBm @ 6.1 GHz. Modification of the LNA, for the simulated, the input return loss (S11) is -13.752 dB; the output return loss (S22) is -12.207 dB; the power gain (S21) is 16.246 dB; the isolation (S12) is -54.828 dB; the NF is 3.675 dB; unconditional stability; the P1dB is -26 dBm @ 6.1 GHz.
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author2 |
Man-Long Her |
author_facet |
Man-Long Her Tseng-Hsun Yuan 袁贈勛 |
author |
Tseng-Hsun Yuan 袁贈勛 |
spellingShingle |
Tseng-Hsun Yuan 袁贈勛 Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
author_sort |
Tseng-Hsun Yuan |
title |
Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
title_short |
Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
title_full |
Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
title_fullStr |
Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
title_full_unstemmed |
Design and Implementation of the Low Noise Amplifier Circuits Using the CMOS 0.18 μm Process for the 13 GHz and the UWB |
title_sort |
design and implementation of the low noise amplifier circuits using the cmos 0.18 μm process for the 13 ghz and the uwb |
publishDate |
2010 |
url |
http://ndltd.ncl.edu.tw/handle/80271620697478888920 |
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