An Associative Cache Design with Conflict Miss Reduction in Power Aware Embedded Systems

• Main Authors: Chien-Fu Chen, 陳建甫
• Other Authors: Ching-Wen Chen
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/85882367937496834475

碩士 === 逢甲大學 === 資訊工程所 === 98 === In the embedded system design, the power-aware issue always catches much of attention. In the factors of consuming power, the cache dominates a great part of power consumption. Therefore, designing a power efficiency cache to reduce the power consumption in embedded systems is an important problem. In the cache design, to have high hit rate, one method is to have high set associative cache. However, the power consumed for accessing a high set associative cache costs times power than accessing a low set associative cache. Although a low set associative cache can reduce the power consumption, the low set associative cache decreases shows high conflict miss rate to result in the increase of power consumption because of increase of accessing memory. Therefore, how to design a low set associative cache with a high hit rate to reduce power consumption is an important problem to design a power-aware embedded system. In this thesis, to have high hit rate and low accessing power, we proposed two designs. The first one is to reduce the conflict miss rate in a low set associative cache. We added an extra small cache that is located between the L1 cache and memory. This added cache could be used as the extension of each set to reduce the conflict miss rate. In addition, to avoid accessing the extra cache if the data belongs to this set is absent from the extra cache, a field is added for each set to record whether the extra cache contains the data belonging to the set. In the second design, we borrow from the blocks of another set to extend the blocks of a set. Because of locality, the usage of sets is not uniform and is always focused on several sets. Accordingly, we use the blocks of sets that are seldom used currently to extend the blocks of sets that are often used to reduce the conflict miss rate. In the simulation, we compared our proposed designs with the victim cache and the traditional cache in terms of the hit rate, the number of memory access times, and power consumed by accessing the cache and memory.