Implementation of Grayscale Image Segmentation Based on FPGA

• Main Authors: Wei-Lun Liang, 梁偉倫
• Other Authors: Deng-Yuan Huang
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/95931289953932338931

碩士 === 大葉大學 === 汽車電子產業研發碩士專班 === 98 === An automatic multilevel thresholding algorithm called HVEM (Histogram-based Valley Estimation Method) based on field programmable gate array (FPGA) is presented for segmenting an image into multiple regions with a similar gray-level distribution. The proposed method is computationally efficient so that it can be easily implemented on an FPGA circuit. A method for determining cluster number is also introduced to automatically choose the proper number of thresholds by estimating all possible valleys in a histogram.The proposed method was compared with the Otsu method on a large number of images. In contrast to HVEM, Otsu’s method has a serious drawback when extending to a multi-threshold version that is very time consuming and also difficult to be implemented on FPGA. Timing simulations show that the designed hardware can run at a speed of 191 MHz (or 1,457 frames per second) for a 256256 gray-level image. This result confirms that the proposed FPGA architecture can achieve the requirements for a real-time image processing system.