Implementation of a LDPC Code for IEEE 802.16e Standard by Using the Eight-core MIPS-like Processor

• Main Authors: Yuan-Wen Huang, 黃垣文
• Other Authors: Ching-Shun Chen
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/48454759370101438682

碩士 === 大葉大學 === 電機工程學系 === 98 === Along with architecture of processor and process’ technology progress, processor’s vendors are not only increasing the frequency of operation, but also turn in to integrate the way to design a chip composed of multi cores in order to improve efficiency. In this study, the eight-core MIPS-like processor is designed by using Verilog hardware description language and algorithmic state machine (ASM), which is able to perform parallel computing and multi-tasking, and is applied to implementation of a LDPC code for IEEE 802.16e standard.In this work, a LDPC code for IEEE 802.16e standard is designed by C program language compiled with MS Visual C++ 2008 to verify its correctness at first. The C design of a LDPC code is further compiled by GCC compiler to generate the MIPS assembly which can be utilized for MIPS-machine simulation by using PCSpim. The generated machine code by PCSpim can be further embedded into the Verilog behavioral model of the eight-core MIPS-like processor. The simulation of Verilog design by ModelSim is with comparison to that by PCSpim for verification, the Verilog behavioral model and the program of the LDPC code are synthesized by using Xilinx software, and programmed into Virtex-5 XC5LX110T FPGA chip. When the signal encoding or decoding process is accomplished, the encoded or decoded data will appear in flash memory finally for further verification.The main contributions of this study are using a HW/SW co-design framework to develop an eight-core MIPS-like processor which is able to perform parallel computing and multi-tasking, and implementation of a LDPC code for IEEE 802.16e standard. Results reveal that CPU computing time of eight-core processor is up to 600% superior (shorter) to that of single-core processor for the simulation of LDPC code in this work.